Computer Organization and Architecture

The fundamental dichotomy between computer architecture and organization, the multi-tier hardware/software abstraction hierarchy, the Von Neumann stored-program model, top-level components (CPU, Memory, I/O, System Bus), the four basic computer functions, and CPU internal microarchitecture (ALU, Control Unit, and Register Transfer Language).

• Unit 1 — Introduction to Computer Organization, Architecture & Top-Level Structure — Chapter PDF
• Lesson 1 — Computer Architecture vs. Computer Organization & The Hardware/Software Abstraction Hierarchy
• Lesson 2 — The Von Neumann Stored-Program Model, Top-Level Structure & Functional Operations
• Lesson 3 — CPU Internal Microarchitecture, Registers & The Execution Engine

The technological evolution of computing across four generations (Vacuum Tubes, Transistors, Integrated Circuits, VLSI), the Princeton IAS machine architecture, Moore's Law and the Power Wall, processor clock speed, CPI, MIPS, the Iron Law of performance, Amdahl's Law speedup limits, and Little's Law in hardware queuing systems.

• Unit 2 — Computer Evolution, Generations & Quantitative Performance Assessment — Chapter PDF
• Lesson 1 — Historical Computer Generations, The Princeton IAS Machine & Moore's Law
• Lesson 2 — Quantitative Processor Performance Metrics, CPI & The Iron Law of Computing
• Lesson 3 — Amdahl's Law, Multi-Core Scaling Limits & Hardware Queuing Theory (Little's Law)

The machine instruction cycle state diagram, micro-operation register transfers, hardware interrupt classes, context switching, multiple interrupt handling (sequential vs nested priority), bus interconnection schemes, multi-tier bus hierarchies, bus arbitration algorithms, and synchronous vs asynchronous handshaking timing protocols.

• Unit 3 — Computer Function, Instruction Cycles, Interrupts & Bus Structures — Chapter PDF
• Lesson 1 — The Machine Instruction Cycle & State Transition Mechanics
• Lesson 2 — Hardware Interrupt Architecture, Context Stacking & Multiple Interrupt Handling
• Lesson 3 — Bus Interconnection Structures, Multi-Tier Hierarchies & Timing Protocols

Characteristics of memory systems, the memory hierarchy pyramid, principle of locality, Average Memory Access Time (AMAT), cache lines vs blocks, direct mapping, fully associative mapping, K-way set-associative mapping, replacement policies (LRU, FIFO, LFU, Random), write policies (write-through vs write-back, write-allocate), and multi-core cache coherency (MESI protocol).

• Unit 4 — Cache Memory Principles, Mapping Functions & Coherency Architectures — Chapter PDF
• Lesson 1 — Memory Hierarchy Fundamentals, Locality of Reference & AMAT Analysis
• Lesson 2 — Cache Mapping Architectures: Direct, Fully Associative & Set-Associative Mapping
• Lesson 3 — Cache Replacement Algorithms, Write Policies & Multicore Cache Coherency

Semiconductor memory cell physics (SRAM vs DRAM), memory cell refresh kinetics, ROM taxonomies, chip organization and address multiplexing (RAS/CAS), error detection and correction principles, Hamming Single Error Correction and Double Error Detection (SEC-DED) codes, syndrome decoding, magnetic disk physical kinematics, rotational latency and seek timing, and Redundant Array of Independent Disks (RAID 0, 1, 5, 6, 10).

• Unit 5 — Semiconductor Main Memory, Error Correction & Storage Architectures — Chapter PDF
• Lesson 1 — Semiconductor Memory Technologies, DRAM Cell Kinetics & Chip Organization
• Lesson 2 — Hardware Error Detection & Correction: Hamming SEC-DED Architecture
• Lesson 3 — External Storage Subsystems, Magnetic Disk Timing & RAID Architectures